Why is the aFrameCheckSequenceErrors counter of the Triple Speed Ethernet (TSE) IP core incremented when alignment errors occur? - Why is the aFrameCheckSequenceErrors counter of the Triple Speed Ethernet (TSE) IP core incremented when alignment errors occur? Description Due to a bug in the Triple Speed Ethernet (TSE) IP core, starting in IP version 13.0 , the aFrameCheckSequenceErrors counter may be incremented when alignment errors occur. A frame with alignment errors should be recognized as an invalid frame, hence aFrameCheckSequenceErrors should not be incremented. Resolution This bug is fixed in IP core version 14.1 and later. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.1 13.0 ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® GX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']