1.8 V LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices - 1.8 V LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices Hi all! I need to receive data from ADC to MAX10 device in my project. The issue is that data rate is 500 Mbps and input clock frequency is 250 MHz. I checked Intel® MAX® 10 FPGA Device Datasheet and found in table 48 that maximum supported frequency is 200 MHz. BUT according to the text in brackets this information is regarding bottom-bank I/O performance pin (I do not exactly understand what it means). I wonder if there is a way to receive 1.8 V LVDS signal on 250 MHz frequency (maybe using other I/O banks). And what should be pin assignment settings for that? Speed grade is 7, dual supply, FBGA256 package. Thanks, Valentyn Replies: Re: 1.8 V LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices Thank you for quick response! Replies: Re: 1.8 V LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices The issue is solved Replies: Re: 1.8 V LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices Hi Valentyn, according to Table 25, standard LVDS receiver (2.5 V supplied) can receive LVDS signal with Vicm > 0.55 at up to 700 Mbps. Means you don't need to refer to 1.8V LVDS receiver. Another point is that most 1.8V ADC (e.g. from ADI) are using standard LVDS (Vocm = 1.25V) rather than subLVDS level (Vocm = 0.9V). Thus 1.8V LVDS might be a suboptimal choice anyway. Regards Frank P.S.: