Error(18090): External memory and PHYLite interfaces must share a common clock and reset signals when constrained to the same I/O column. - Error(18090): External memory and PHYLite interfaces must share a common clock and reset signals when constrained to the same I/O column. Description Due to a problem in the Intel® Quartus® Prime software version 19.2 or earlier, you may see the fitter error message when you aren't sharing the same clock and reset signals across multiple Intel Arria® 10 EMIF IPs in the same I/O column. This message is incorrect, and you can follow the guidelines described in the Intel® Arria® 10 EMIF IP User Guide. To place multiple interfaces in the same I/O column, you must ensure that each interface's global reset signals (global_reset_n) come from the same input pin or signal. Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting 1607598066 False ['External Memory Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']