Why does the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps design examples send an incorrect number of packets? - Why does the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps design examples send an incorrect number of packets? Description When using the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps design examples operating in both fixed mode and increment mode transmit an incorrect number of packets. The observed transmit pattern shows that the IP is only sending half the number of expected packets. Resolution This problem has been fixed starting in version 19.3 of the Intel® Quartus® Prime Pro edition software. Custom Fields values: ['novalue'] Troubleshooting 1409630957 False ['25G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.2 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']