Creating a System Design with Platform Designer: Getting Started - Same Course in Japanese: Qsysを使用したシステム・デザインの生成方法 28 Minutes This training is part 1 of 2. The Platform Designer system integration tool, formerly known as Qsys, saves design time and improves productivity by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. In this training, you'll learn how to begin the creation of a system design using the Platform Designer user interface. You'll create a new system design file and add components from the Platform Designer IP Catalog to the design. This training includes a lab exercise with instructions and files that are designed for the Quartus® Prime software, version 17.1, and the Cyclone® V GX FPGA Starter Kit from Terasic. Course Objectives At course completion, you will be able to: Create a system design in the Platform Designer user interface Incorporate your Platform Designer system into an Quartus® Prime project for compilation Skills Required Familiarity with FPGA/CPLD design flow Working knowledge of the Quartus® Prime software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OQSYSCREATE. FPGA_OQSYSCREATE. <p>Creating a System Design with Platform Designer: Getting Started</p>