Why does my F-Tile Ethernet Multirate IP variant with the “Enable auto-negotiation and link training” parameter enabled and the “Link fault generation” parameter set to “Bidirectional” fail to complete “auto-negotiation and link training”? - Why does my F-Tile Ethernet Multirate IP variant with the “Enable auto-negotiation and link training” parameter enabled and the “Link fault generation” parameter set to “Bidirectional” fail to complete “auto-negotiation and link training”? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile Ethernet Multirate IP variant with the “ Enable auto-negotiation and link training ” parameter enabled and the “ Link fault generation ” parameter set to “ Bidirectional ” will fail to complete auto-negotiation and link training. Resolution To work around this problem, perform the following steps: For hardware support, open the <variant_name>_base_profile_dr_sip_1.sv file located at <ethernet variant name>/eth_f_dr_1300/synth/ directory. For simulation support, open the <variant_name>_base_profile_dr_sip_1.sv file located at <ethernet variant name>/eth_f_dr_1300/sim/ directory. Change the following RTL code starting at line 4872 FROM //ehip reset always @(posedge i_reconfig_clk) begin if (reconfig_reset_sync || counter_expired[port_idx] ) begin ehip_rst[port_idx] <= 1'b0; end else if(rf_in_progress_edge[port_idx]) begin ehip_rst[port_idx] <= 1'b1; end end TO if (ENABLE_ANLT) begin:NO_EHIP_RESET_ANLT assign ehip_rst[port_idx] = 1'b0; end else begin : EHIP_RESET_NO_ANLT //ehip reset always @(posedge i_reconfig_clk) begin if (reconfig_reset_sync || counter_expired[port_idx] ) begin ehip_rst[port_idx] <= 1'b0; end else if(rf_in_progress_edge[port_idx]) begin ehip_rst[port_idx] <= 1'b1; end end end Recompile your design This problem was fixed in version 24.3.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16025552459 False ['F-Tile Ethernet Multirate IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.3 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']