Do I need to trigger a reset before a speed change on the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP USXGMII TX and RX data paths? - Do I need to trigger a reset before a speed change on the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP USXGMII TX and RX data paths? Description When using the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP in USXGMII operating mode, it is not required to trigger a reset on the TX and RX datapaths since the transceivers will keep running at a 10.3125Gbps rate. Make sure that the MAC TX and RX datapaths are idle, with no packet transmission, before performing the speed change. Resolution This information is scheduled to be updated in a future release of the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide. Custom Fields values: ['novalue'] Errata 15011257931 False ['Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.3 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']