Generating a design in platform designer - Generating a design in platform designer I am trying to generate a design in the platform designer with just a clock module and HPS. I get the following message: Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga_lite/20.11/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally followed by around 100 lines starting with the "Error: border: Error during execution of script generate_hps_sdram.tcl:" Tried Quartus lite 20.1 and 20.1.1 but always the same error. I saw that this error happens also in 18.1 ( https://www.intel.com/content/www/us/en/support/programmable/articles/000080619.html ) and it says it is planned to be fixed in future release. When/which version of quartus will that be? Replies: Re: Generating a design in platform designer One of the links in the KDB helped. https://www.intel.com/content/www/us/en/support/programmable/articles/000074066.html Replies: Re: Generating a design in platform designer Hi, Please try below KDB: https://www.intel.com/content/www/us/en/support/programmable/articles/000086780.html Replies: Re: Generating a design in platform designer Yes, it is the Cyclone V (5CSEM). The design was originally implemented with Quartus 18 so it is a working solution (generating a new design with 20.1 doesn't work also). Replies: Re: Generating a design in platform designer What is your target device and how do you have the memory interface set up with respect to the HPS in Platform Designer (PD)? A screenshot of your PD system would be helpful. The only device I can think of that would be SoC and supported in Lite would be Cyclone V.