Why do I see stability problems with the JESD204C design examples which use the F-Tile JESD204C FPGA IP in external loopback? - Why do I see stability problems with the JESD204C design examples which use the F-Tile JESD204C FPGA IP in external loopback? Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.3, the JESD204C design examples which use the F-Tile JESD204C FPGA IP in external loopback may experience stability problems. Depending on the exact variant you are using, these problems might manifest themselves as emb_unlock_err, sh_unlock_err, rx_gb_underflow_err, cmd_par_err, invalid_eoemb, invalid_eomb, invalid_sync_header and lane_deskew_err events. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 22.3. Download and install p atch 0.11 from the appropriate link below, then re-generate your programming file. Download patch 0.11fw for Windows (Quartus-22.3-0.11fw-windows.exe) Download patch 0.11fw for Linux (Quartus-22.3-0.11fw-linux.run) Download the Readme for patch 0.11fw (Quartus-22.3-0.11fw-readme.txt) This problem is fixed beginning with the Quartus Prime Pro Edition Software version 22.4. Custom Fields values: ['novalue'] Troubleshooting 15011902126 False ['F-Tile JESD204C IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 22.3 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']