O-RAN FPGA IP - Altera O-RAN IP delivers a flexible, standards-compliant fronthaul interface for 5G and LTE systems using the 7-2x functional split. Supporting both control and user planes per O-RAN-FH.CUS.0-v03.00,… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA The O-RAN IP provides delay management service to ensure that it receives correct data over the fronthaul interface despite packet delay variation (PDV). The IP refers to concept and latency models from the eCPRI specification. The IP manages transmission and receiver windows, which you can place relative to the air interface based on predefined or measured transport delay. The IP exchanges RU parameters and network characteristic over M-plane messages. The IP monitors and counts packets transmitted or received out of the window to warn the other node and discard them if necessary. The IP also transmits and receives non-delay managed U-plane traffic for which normal windows are not applicable. Defense Wireless AI/HPC (DCO) ASIC Emulation ASIC Prototyping ATE Automotive (Passenger Vehicles) Broadcast Studio Cable Access Carrier Access CDNs (DCO) Communication Tester Gaming IaaS/PaaS (DCO) Lab/Life Sciences Multi-Functional Printer Networking (DCO) Non-Automotive Transportation Non-Imaging Patient Devices Other Access Other Consumer Other Medical Other Test RF Instrumentation Storage (DCO) Transportation Infrastructure (non-charging) O-RAN FPGA IP Key Features Support for CAT-A RU (up to 8 spatial streams) Offering Brief No No No Yes Verilog VHDL Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Yes Yes Offering Brief Production a1JUi000007q141MAA What's Included Encrypted Verilog source code Ordering Information IP-ORAN-FH Digikey Mouser a1JUi000007q141MAA Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2026-04-21T12:58:33.000+0000 Altera O-RAN IP delivers a flexible, standards-compliant fronthaul interface for 5G and LTE systems using the 7-2x functional split. Supporting both control and user planes per O-RAN-FH.CUS.0-v03.00, it simplifies DU-RU integration, accelerates development, and ensures interoperability in disaggregated, open RAN architectures. Altera Solutions