Why does a fitter error occur relating to the failure to find a legal placement for periphery components when using the GTS JESD204B IP when transceiver bank pins are utilized together with HVIO pins? - Why does a fitter error occur relating to the failure to find a legal placement for periphery components when using the GTS JESD204B IP when transceiver bank pins are utilized together with HVIO pins? Description When running the Quartus® Prime Pro fitter plan stage on the GTS JESD204B IP with tx_serial_data/rx_serial_data pins assigned at corner transceiver banks 1A, 4A or 4C, the following error might occur: This fitter error states that it cannot place either 1 SM_HSSI_PLD_CHNL_DP or 1 IPFLUXTOP_UXTOP_WRAP . This is due to shared clocking resources between a corner GTS transceiver bank and an adjacent HVIO bank. These clocking resources are muxed together between the transceiver bank and HVIO bank (Refer to the section “Shared Clocking Resources between the GTS Transceiver Bank and HVIO bank” in the GTS Transceiver PHY User Guide for further information). As an example, when using transceiver bank 4C together with HVIO bank 6D. The following clocks are used: Clock Bank IP tx_clkout 4C (XCVR) GTS JESD204B tx_clkout2 4C (XCVR) GTS JESD204B rx_clkout 4C (XCVR) GTS JESD204B rx_clkout2 4C (XCVR) GTS JESD204B SourceSync Clk1 6D (HVIO) HPS From the table, there are 5 clock resources that are required in the design, but only 4 muxes are available to be allocated for each clock. Hence, the issue occurs. This issue only occurs when there is an adjacent HVIO bank attached to it and occurs on both Agilex™ 3 FPGA and Agilex™ 5 FPGA devices. Resolution The solution is to free-up two clocks within GTS JESD204B IP so that the mux is available to be used by the HVIO bank. Altera recommends installing the following patch in the Quartus® Prime Pro Edition Software version 24.3.1 or 25.1: 24.3.1: Download patch for Windows (quartus-24.3.1-1.09-windows.exe) Download patch for Linux (quartus-24.3.1-1.09-linux.run) Download Readme for patch (quartus-24.3.1-1.09-readme.txt) 25.1: Download patch for Windows (quartus-25.1-0.08-windows.exe) Download patch for Linux (quartus-25.1-0.08-linux.run) Download Readme for patch (quartus-25.1-0.08-readme.txt) After installing the patch, regenerate the GTS JESD204B FPGA IP through IP parameter editor and rerun the full compilation of the design. This problem will be fixed in a future version of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15017457857 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']