Why do I see a low fmax on a floating-point adder on Arria 10, even when the adder is fully pipelined? - Why do I see a low fmax on a floating-point adder on Arria 10, even when the adder is fully pipelined? Description This problem affects DSP Builder designs targeting Arria 10 DSP blocks’ floating-point mode. You may see a long setup time on one of the input pins to the DSP block in SP_ADD mode as a ~2.5ns setup time for an input pin ax[30] on the DSP block. This setup time reduces fMAX below 276MHz.. Resolution This problem has no workaround. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']