Why does the F-Tile PMA/FEC Direct PHY FPGA IP variant fail Quartus® Support Logic Generation with the Enable TX double width transfer and Enable RX double width transfer parameters selected, and the RX core interface FIFO mode option is set to Elastic? - Why does the F-Tile PMA/FEC Direct PHY FPGA IP variant fail Quartus® Support Logic Generation with the Enable TX double width transfer and Enable RX double width transfer parameters selected, and the RX core interface FIFO mode option is set to Elastic? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the F-Tile PMA/FEC Direct PHY FPGA IP will fail to pass Quartus® Support Logic Generation when the Enable TX double width transfer and Enable RX double width transfer parameters are selected, and the RX core interface FIFO mode optio n is set to Elastic ? Resolution There is no workaround for this problem. This problem has been fixed starting in version 24.3 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16023671866 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']