Why does the SDM experience a hang when performing back-to-back reconfigurations on Agilex™ FPGA devices? - Why does the SDM experience a hang when performing back-to-back reconfigurations on Agilex™ FPGA devices? Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.4 and later, the SDM may hang during back-to-back reconfiguration . This issue can occur in all configuration modes . The probability of occurrence is very low , as it depends on several factors such as design seed, utilization, data rate, configuration source, compression ratio, and others. When this issue occurs: In AVST mode , AVST_READY is deasserted (=low) in the middle of reconfiguration and remains low. nSTATUS is not deasserted (=low) , therefore, no configuration error is flagged. CONFIG_STATUS continues to indicate that configuration is ongoing, with no error detected. This issue may affect Agilex™ 3, 5, and 7 FPGA devices. Resolution To work around this problem: Perform reconfiguration via JTAG , which recovers from the issue. This problem is planned to be fixed in Quartus® Prime Pro Edition Software version 25.1.1 . The fix increases the configuration time maximum up to 1%. For existing versions, download and install the corresponding patch to fix the problem: Quartus Prime Pro v24.3.1 → Patch 1.15fw Quartus Prime Pro v24.3 → Patch 0.22fw Quartus Prime Pro v23.3 → Patch 0.50fw Custom Fields values: ['novalue'] Troubleshooting 14023796018 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1.1 22.4 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']