Why does the F-Tile Ethernet Hard IP Example Design simulation for the Multi-Instance variant generated by the Quartus® Prime Pro Edition software version 25.1 fail? - Why does the F-Tile Ethernet Hard IP Example Design simulation for the Multi-Instance variant generated by the Quartus® Prime Pro Edition software version 25.1 fail? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1, the F-Tile Ethernet Hard IP Example Design for the Multi-Instance variant may fail to simulate. This is due to a single-bit reset signal, ' d_rst_n ', driving a multi-bit reset signal, ' rst_n ', in the F-Tile Ethernet Hard IP Example Design for Multi-Instance variant. This does not affect the F-Tile Ethernet Hard IP Example Design for the single Instance variant. Resolution Follow the steps below to work around this problem in the Quartus® Prime Pro Edition software version 25.1. 1) Once the Ethernet example design for the multi-instance variant is generated, the example design folder will contain these four items. 1. Ex_<speed>G 2. Ex_<speed>G.ip 3. Example_testbench 4. hardware_test_design 2) Go to hardware_test_design folder and open eth_f_hw.v file 3) In this eth_f_hw.v file search for the following line, " assign rst_n = i_rst_n & d_rst_n; " 4) Replace this line with the following lines and save the file. genvar i; generate for (i=0; i < INSTANCE_NUM; i = i+1) begin: reset_n assign rst_n[i] = i_rst_n[i] & d_rst_n; end endgenerate" 5) Run simulation as usual. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 16027068833 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']