How to generate a netlist when the design includes encrypted sources - How to generate a netlist when the design includes encrypted sources I would like to ship my design to a customer as an encrypted netlist, however I am unable to create the netlist after a successful run, because my design includes encrypted RTL (unable to change this). I am running the following command (after running synthesis and P&R): quartus_eda my_project --simulation --format=vhdl --tool=modelsim -c my_project_revision I get the following error: Error (18580): Cannot generate netlist output files because the design includes encrypted source files: "/path/to/encrypted/rtl/file.vhdp" I see here that this was planned to be possible in "future" Quartus Prime updates, but I am using 26.1 and no such update has been made. I have also attempted to run the following command, with the exact same result: quartus_eda my_project --resynthesis --tool=modelsim Any help would be appreciated; perhaps this is plainly impossible, or perhaps there is some work-around. Thank you! Replies: Re: How to generate a netlist when the design includes encrypted sources Currently there's no workaround. Replies: Re: How to generate a netlist when the design includes encrypted sources Thanks, is there any work-around for this limitation? Other than removing the encrypted source files? Replies: Re: How to generate a netlist when the design includes encrypted sources Hi, Yes, you're right. That's plainly impossible. Based on internal sync message, that error is expected behaviour and not a bug