When using the Intel® FPGA P-Tile Avalon® streaming IP for PCI* Express, why is an error seen when "Enable Completion Timeout Interface" is selected? - When using the Intel® FPGA P-Tile Avalon® streaming IP for PCI* Express, why is an error seen when "Enable Completion Timeout Interface" is selected? Description Due to a problem with the Intel® FPGA P-Tile Avalon® streaming IP for PCI* Express, and error of the form shown below will be seen if the option " Enable Completion Timeout Interface " is selected in the IP GUI. Error: intel_pcie_ptile_ast_0.dummy_user_avmm_rst has an associatedClock of "p0_hip_reconfig_clk" which could not be found This is due to the completion timeout interface being incorrectly associated with the hip_reconfig_clk . This error prevents the IP from being generated. Resolution In v20.1 of the Intel® Quartus® Prime Pro Edition of software, no workaround to this problem exists, generate the IP with the option " Enable Completion Timeout Interface " disabled. This problem has been fixed starting in v20.2 of the Intel® Quartus® Prime Pro Edition of software. Custom Fields values: ['novalue'] Troubleshooting 14011160563, 14011160835 True ['Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.2 20.1 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']