DisplayPort RX Video Start of Line and Start of Frame Signals Asserted More Than 1 Clock Cycle - DisplayPort RX Video Start of Line and Start of Frame Signals Asserted More Than 1 Clock Cycle Description The DisplayPort RX video start of line and start of frame signals ( rx_vid_sol and rx_vid_sof ) stay asserted for more than 1 clock cycle. This issue is caused by the change in the signals\' FIFO control behavior. If your video processing IP core detects the rx_vid_sol and rx_vid_sof signals\' level, it will process the video data incorrectly because these signals are misaligned. If your video processing IP core detects the rising edge of the rx_vid_sol and rx_vid_sof signals, there will be no impact on the video processing behavior. Resolution To work around this issue, add a rising detect logic for these two signals after the DisplayPort RX core. This issue is fixed in version 15.1 of the DisplayPort IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 15.1 15.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']