User controlled burst refresh - User controlled burst refresh Hi, I have a problem regarding DDR3 EMIF IP can't bursting user control refresh. I am debugging my EMIF test design on Cyclone 10 GX development board. The situation is that it takes long time to get mmr_refresh_ack response. Below is my environment: Quartus Prime Pro 23.2 on Windows 11 External Memory Interfaces Intel Cyclone 10 FPGA IP, altera_emif_c10 19.1.1 Cyclone 10 GX FPGA Development Kit (Power Solution 1) DK-DEV-10CX220-A Cyclone 10 GX 10CX220YF780E5G First of all, I have a question about the description of the user guide. I would like to fix my design after question was solved. I am referring External Memory Interfaces Cyclone 10 GX FPGA IP User Guide Updated for Quartus Prime Design Suite: 24.1 IP Version: 19.1.2. 1. In page 84, Table 4.4.13 for mmr_refresh_req states that Controller clears this bit to 0 when the refresh is executed. This is inconsistent for the description: Page 223, 9.4.6.1 Back-to-Back User-Controlled Refresh Usage: The waveform instruct user to clear mmr_refresh_req before set mmr_refresh_req again at reference time (5). I guess this waveform explains back-to-back user controlled refresh so, the next refresh request is expected tRFC after reference time (4). My question is: Should I clear the mmr_refresh_req register before back-to-back next refresh request? 2. In page 223, --- Note: If you enable the auto-precharge control, you must ensure that the average periodic refresh requirement is met, because the controller does not issue any refreshes until you instruct it to. --- What happens if I disable the auto-precharge control? In this case, are both IP planned refresh and user controlled refresh happens? 3. There are two enable user refresh controls in the user guide: 1) IP parameter of Enable User Refresh Control 2) cfg_user_rfsh_en register inside the IP What is the relationship of them? Does the IP parameter define initial state of cfg_user_rfsh_en register? Is the logical AND condition needed for the user controlled refresh? 4. In page 78, table 4.4. Cyclone 10 GX Memory Mapped Register (MMR) Tables: The cfg_user_rfsh_en register is missing. Do I need to handle this register? Masaru Replies: Re: User controlled burst refresh I found three incorrect explanations of section 9.4.6 User-Controlled Refresh. 1. Page 223, Note:, "If you enable the auto-precharge control,..." should be "If you enable the user controled refresh,...". 2. Page 223, 9.4.6.1 Back-to-Back User-Controlled Refresh Usage, Step 1 to write the cfg_user_rfsh_en register should not be done. If we write to the register, we do not receive acknolegement for a long time at step 3. 3. Page 223, Fighre 87, the tRFC mesurement should start with timing (2) not with (4). By my interpretations, my design works fine for back to back user contlloled refresh. altera should fix section 9.4.6 User-Controlled Refresh. Masaru Replies: Re: User controlled burst refresh Adzim, For my point 4 and 1, altera should provide correct information to users. If the cfg_user_rfsh_en register is not needed to access from user logic as you said, altera should revise Page 223, Section 9.4.6.1 up to correct waveform and put its explanation. I do not wat to try something and discard it back and forth. Does someone from altera can answer my question points? Regards, Masaru Replies: Re: User controlled burst refresh Hi MamaSaru , " Is "it" referring cfg_user_rfsh_en register? " -Yes Maybe you also can try to assert read for one clock cycle only instead of assert read until readdatavalid. Regards, Adzim Replies: Re: User controlled burst refresh For my point 4, you said: >I don't think you need to enable it from the user logic. Is "it" referring cfg_user_rfsh_en register? Replies: Re: User controlled burst refresh Hi Masaru, When user control refresh is enabled, user has complete control and responsible to provide sufficient refresh to memory. The statement in EMIF UG mentioned it here: https://docs.altera.com/r/docs/683663/24.1/external-memory-interfaces-cyclone-10-gx-fpga-ip-user-guide/intel-cyclone-10-gx-emif-ip-ddr3-parameters-controller The IP should enable the user control refresh already. I don't think you need to enable it from the user logic. Regards, Adzim Replies: Re: User controlled burst refresh Hi Adzim, Thank you for your reply. 1. >- No the IP should handle it. So, the section "9.4.6.1. Back-to-Back User-Controlled Refresh Usage" should be revised not to clear the mmr_refresh_req register. 2. >- You should control the refresh since the IP doesn't issue the refresh if user controlled refresh is enabled. No, original statement said, "If you enable the auto-precharge control,". Is this statement correct? 3. >- You don't have to care about that. Only use the MMR interface. Do you mean the Enable User Refresh IP parameter doesn't affect at all? Can I run user control refresh under IP parameter is off? 4. - No need. Do you mean I don't need to handle cfg_user_rfsh_en register? I am confused about your answer. Masaru Replies: Re: User controlled burst refresh Hi Masaru, 1. " Should I clear the mmr_refresh_req register before back-to-back next refresh request? " - No the IP should handle it. 2. " What happens if I disable the auto-precharge control? In this case, are both IP planned refresh and user controlled refresh happens? " - You should control the refresh since the IP doesn't issue the refresh if user controlled refresh is enabled. 3. " What is the relationship of them? Does the IP parameter define initial state of cfg_user_rfsh_en register? Is the logical AND condition needed for the user controlled refresh? " - You don't have to care about that. Only use the MMR interface. 4. " Do I need to handle this register? " - No need. Regards, Adzim