Why doesn't the lock-to-reference (LTR) mode work for F-Tile PMA/FEC Direct PHY Intel® FPGA IP? - Why doesn't the lock-to-reference (LTR) mode work for F-Tile PMA/FEC Direct PHY Intel® FPGA IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 and earlier, the lock-to-reference (LTR) mode can not be enabled for F-Tile PMA/FEC Direct PHY Intel® FPGA IP. Resolution There is no workaround for PMA type FGT with PAM4 and PMA type FHT with PAM4/NRZ. However, there is a workaround for physical medium attachment (PMA) type FGT with nonreturn-to-zero (NRZ) to avoid this problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 and earlier. The following steps are an example of a signal-lane design: Add the following QSF assignments in the project .qsf file: set_instance_assignment -name HSSI_PARAMETER "flux_mode=FLUX_MODE_BYPASS" -to rx_serial_data[0] -entity top set_instance_assignment -name HSSI_PARAMETER "flux_mode=FLUX_MODE_BYPASS" -to tx_serial_data[0] -entity top set_instance_assignment -name HSSI_PARAMETER "engineered_link_mode=ENABLE" -to rx_serial_data[0] -entity top set_instance_assignment -name HSSI_PARAMETER "engineered_link_mode=ENABLE" -to tx_serial_data[0] -entity top set_instance_assignment -name HSSI_PARAMETER "rx_adapt_mode=RX_ADAPT_MODE_STATIC_EQ" -to rx_serial_data[0] -entity top Note: Replace "rx_serial_data[0]" with the receiver signal of your design. Replace "tx_serial_data[0]" with the transmitter signal of your design. Replace "top" with the top-level entity name of your design. For a multi-lane design, you should have the above 5 assignments for every lane. 2. Recompile and program your design. 3. Through the Datapath Avalon® Memory-Mapped Interface, write CSR rx_ignore_locked2data register 0x818[0] with value 1'b1 4. Assert rx_reset 5. Through the PMA Avalon Memory-Mapped Interface, write the following registers with value 1'b1: 0x41680[28] 0x41680[24] 0x41580[31] 0x41580[30] 6. De-assert rx_reset This problem will be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14017001500 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 21.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']