How do I tell the difference between a local fault condition and valid RX data when using the Stratix® 10 E-Tile Hard IP for Ethernet FPGA IP configured in PCS FEC status without the MAC? - How do I tell the difference between a local fault condition and valid RX data when using the Stratix® 10 E-Tile Hard IP for Ethernet FPGA IP configured in PCS FEC status without the MAC? Description Due to a problem in the Quartus® Prime Software version 18.1 and earlier, the signal o_rx_pcs_fully_aligned is not exposed outside of the Stratix® 10 E-Tile Hard IP for Ethernet FPGA IP when configured in PCS FEC status without the MAC. Resolution To work around this problem, the user must properly decode the RX MII port in order to determine a local fault condition. The pseudo-code snippet below illustrates such a decoder: If (mii_data == 0x9C000001) ( • local fault pattern received on mii_data (RX) • remote fault is expected on the TX serial data ) else if (mii_data != 0x9C000001 && mii_valid==1) • mii_data is a valid XGMII block else if (mii_data != 0x9C000001 && mii_valid==0) • ignore mii_data as it is not valid XGMII data endif This problem is scheduled to be fixed in a future release of the Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting FB: 597593; False ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 18.1 ['Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']