DE10 Lite setting pins from VErilog RTL - DE10 Lite setting pins from VErilog RTL In my design, the GPIOs need to be used to connect to external host (Raspberry PI (aka RPI) in this case). The GPIOs connector of the DE10 lite will be connected to the RPI connector. Some are inputs, some are outputs. I prefer to set the pins assignment from the Verilog file, to allow easier maintenance of the project over time. Gemini AI suggested to use: (* location = "PIN_AA13" *) assign gpio_out1 = gpio_out1_int; Yet the compiler reports: Warning (10335): Unrecognized synthesis attribute "location" at ../Verilog/MAC_proj.v(142) Gemini claims I might not be using Quartus Synthesis tool. Could it be? How can I check and set it correctly? Replies: Re: DE10 Lite setting pins from VErilog RTL Thank you for acknowledging the solution provided. I'm pleased to know that your question has been addressed. Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you and have a great day! Best Regards, Richard Tan Replies: Re: DE10 Lite setting pins from VErilog RTL I think I am all set. Thank you for the good support. Replies: Re: DE10 Lite setting pins from VErilog RTL I believe all your inquiries has been answered. Do you have any further question? Regards, Richard Tan Replies: Re: DE10 Lite setting pins from VErilog RTL True, yet in this case I need to modify accordingly the qsf file naming, to maintain the IO mapping. Replies: Re: DE10 Lite setting pins from VErilog RTL Just edit the top-level. And you need to give unique names to inputs vs. outputs (GPIO_IN vs. GPIO_OUT perhaps). Replies: Re: DE10 Lite setting pins from VErilog RTL When compiling this: input [ 7 : 0 ] GPIO, input [ 15 : 8 ] GPIO The error is: Error (10134): Verilog HDL Module Declaration error at MAC_proj.v(37): port "GPIO" is declared more than once About the pins assignment: You have a good point. I assumed it was done due to naming, yet now I can see the QSF has these names inside. Here is the golden top: //======================================================= // This code is generated by Terasic System Builder //======================================================= module DE10_LITE_Golden_Top( //////////// CLOCK ////////// input ADC_CLK_10, input MAX10_CLK1_50, input MAX10_CLK2_50, //////////// SDRAM ////////// output [12:0] DRAM_ADDR, output [1:0] DRAM_BA, output DRAM_CAS_N, output DRAM_CKE, output DRAM_CLK, output DRAM_CS_N, inout [15:0] DRAM_DQ, output DRAM_LDQM, output DRAM_RAS_N, output DRAM_UDQM, output DRAM_WE_N, //////////// SEG7 ////////// output [7:0] HEX0, output [7:0] HEX1, output [7:0] HEX2, output [7:0] HEX3, output [7:0] HEX4, output [7:0] HEX5, //////////// KEY ////////// input [1:0] KEY, //////////// LED ////////// output [9:0] LEDR, //////////// SW ////////// input [9:0] SW, //////////// VGA ////////// output [3:0] VGA_B, output [3:0] VGA_G, output VGA_HS, output [3:0] VGA_R, output VGA_VS, //////////// Accelerometer ////////// output GSENSOR_CS_N, input [2:1] GSENSOR_INT, output GSENSOR_SCLK, inout GSENSOR_SDI, inout GSENSOR_SDO, //////////// Arduino ////////// inout [15:0] ARDUINO_IO, inout ARDUINO_RESET_N, //////////// GPIO, GPIO connect to GPIO Default ////////// inout [35:0] GPIO ); //======================================================= // REG/WIRE declarations //======================================================= //======================================================= // Structural coding //======================================================= endmodule Replies: Re: DE10 Lite setting pins from VErilog RTL Could you share the design for the golden top? You mentioned that the pin is assigned—could you check if it’s assigned through the .qsf file or the RTL? If it’s assigned in the RTL, what does it look like? Also, what is the exact error message shown by the compiler? Please paste the error message or provide a screenshot for reference Regards, Richard Tan Replies: Re: DE10 Lite setting pins from VErilog RTL I think there is a way to control pinout from the RTL source file. There is a "golden top" within "CD-ROM" download files. All the pins are listed, I assume these are keywords that guide the pin planner. The problem I faced was with definition of IOs: GPIO[35:0] was defined as INOUT. When trying to define part of it as Input, and part as output (i.e input GPIO[7:0]; output GPIO[15:8];) the compiler reported error fo double definition of GPIO. Replies: Re: DE10 Lite setting pins from VErilog RTL Dropping a note to ask if my last reply was helpful to you. Do you need any further assistance from my side? Regards, Richard Tan Replies: Re: DE10 Lite setting pins from VErilog RTL Pin assignment is not possible through RTL. You need to use 'set_location_assignment' in the .qsf file. Check the User Guide below for further details. https://www.intel.com/content/www/us/en/docs/programmable/683432/21-3/tcl_pkg_project_ver_7.0_cmd_set_location_assignment.html Alternatively, you could use the Pin Planner tool by go to Assignments > Pin Planner . Regards, Richard Tan Replies: Re: DE10 Lite setting pins from VErilog RTL I don't think that's a valid synthesis attribute. You have to store location assignments in the .qsf. This is a list of synthesis attributes: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir.htm