Is there any known issue using the On-chip parallel termination (RT) with calibration in Stratix III, Stratix IV, and Arria II GZ devices in the Quartus II software version 11.0 and 11.0 SP1? - Is there any known issue using the On-chip parallel termination (RT) with calibration in Stratix III, Stratix IV, and Arria II GZ devices in the Quartus II software version 11.0 and 11.0 SP1? Description Yes, there is an issue for the OCT R T with calibration setting in the configuration file generated by the Quartus® II software version 11.0 and 11.0 SP1. Although the OCT R T with calibration is enabled for the specific pins in assignment editor and the setting is reflected in the compilation report, the Quartus II software does not correctly enable the configuration bits for OCT R T setting in the configuration file. This issue only impacts Stratix® III, Stratix IV, and Arria II GZ device families. It will be fixed in the next release of the Quartus II software. To overcome this issue in Quartus II software version 11.0 and 11.0SP1, you need to install the following patch and perform a full compilation of your design: Download the Quartus II software version 11.0 Linux (.tar) patch 0.28 Download the Quartus II software version 11.0 Windows (.exe) patch 0.28 Download the Quartus II software version 11.0 ReadMe for patch 0.28 Download the Quartus II software version 11.0 SP1 Linux (.tar) patch 1.10 Download the Quartus II software version 11.0 SP1 Windows (.exe) patch 1.10 Download the Quartus II software version 11.0 SP1 ReadMe for patch 1.10 Related Articles Is there any known issue using the On-chip parallel termination (RT) with UniPHY IP ? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices', 'Stratix® III FPGAs'] ['novalue'] ['novalue'] ['novalue']