Why does the SPI (4 Wire Serial) IP report hold violations in Timing Analyzer? - Why does the SPI (4 Wire Serial) IP report hold violations in Timing Analyzer? Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see hold timing violations during Timing Analyzer when using the SPI (4 Wire Serial) IP. The SPI IP generates an SDC file that includes the following incorrect constraint: create_generated_clock -name spi_gen_clk -divide_by {4} -source [get_pins $ipath|tx_holding_primed|clk] [get_pins $ipath|SCLK_reg|q] This constraint can cause hold timing violations between the spi_gen_clk and the external clock, making timing closure difficult—especially in designs with multiple SPI instances. This problem does not occur in the Quartus® Prime Standard Edition Software, where such an SDC constraint is not generated for the SPI IP. Resolution To work around this problem: Remove the incorrect constraint from the IP-generated SDC file: Delete the following line: create_generated_clock -name spi_gen_clk -divide_by {4} -source [get_pins $ipath|tx_holding_primed|clk] [get_pins $ipath|SCLK_reg|q] This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15018844118 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1.1 ['Agilex™ 3 FPGAs and SoCs', 'Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']