Incorrect Transceiver Receive Clock for 1000BASE-X/SGMII PCS in 1000BASE-X Mode - Incorrect Transceiver Receive Clock for 1000BASE-X/SGMII PCS in 1000BASE-X Mode Description This errata affects the Triple-Speed Ethernet MegaCore function. The phase compensation FIFO read clock in the transceiver is not driven by the same clock that drives the 1000BASE-X PCS receiver logic. This causes incorrect timing analysis and receive data error. This issue affects variants of MAC function with 1000BASE-X PCS function and embedded PMA. Resolution This issue has no workaround.This issue is fixed in version 12.0 of the Triple-Speed Ethernet MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Ethernet'] ['FPGA Dev Tools Quartus II Software'] 12.0 11.1 ['Arria® II FPGAs', 'Arria® II GX FPGA'] ['novalue'] ['novalue'] ['novalue']