Why can't I disable background calibration for the 25G Ethernet Intel® Stratix® 10 IP for the Intel® Stratix® 10 H-Tile production FPGAs? - Why can't I disable background calibration for the 25G Ethernet Intel® Stratix® 10 IP for the Intel® Stratix® 10 H-Tile production FPGAs? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 18.1.2, 18.1.1, and 18.1, when using the soft 25G Ethernet Intel® Stratix® 10 IP Core for H-tile production devices, you might not be able to disable background calibration by writing 0 to register 0x542[0] of the transceiver control and status registers. Resolution To work around this problem, follow these steps: Locate the Intel® Quartus® Prime Software IP file (.ip file) of the 25G Ethernet Intel® Stratix® 10 IP. Search for SYNOPT_AUTO_ADAPTATION parameter in the .ip file. Change the <ipxact:value> value from 1 to 0. <ipxact:parameter parameterId="SYNOPT_AUTO_ADAPTATION" type="int"> <ipxact:name>SYNOPT_AUTO_ADAPTATION</ipxact:name> <ipxact:displayName>Enable auto adaptation triggering for RX PMA CTLE/DFE mode</ipxact:displayName> <ipxact:value>0</ipxact:value> Regenerate the 25G Ethernet Intel® Stratix® 10 IP. Recompile the design in the Intel® Quartus® Prime Pro Edition Software. Write 0x0 into register 0x542[0] of the transceiver control and status registers using the transceiver reconfiguration Avalon® memory mapped interface to disable background calibration. Refer to the Background Calibration section of the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide for more information about how to enable and disable background calibration. Perform reconfiguration register accesses. Enable background calibration by writing 0x1 to register 0x542[0]. If Adaption is desired, refer to Adaptation Control - Start section of the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide for more information about how to start signal adaptation. Custom Fields values: ['novalue'] Troubleshooting 1409009018 True ['25G Ethernet IP', 'Ethernet', 'H-tile Hard IP for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']