Introduction to Platform Designer - Same Course in Simplified Chinese: Altera® 平台设计工具Platform Designer简介 Same Course in Japanese: Qsys 基礎編 30 Minutes The Platform Designer system integration tool saves design time and improves productivity by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. In this training, you will receive an introduction to system design and get an overview of the Platform Designer system integration tool and its key features in the Altera® Quartus® Prime software. You will learn about the benefits of using standard interfaces in your FPGA design process and about the custom-generated, Network-on-a-Chip based, high-performance interconnect created to link these interfaces together. Course Objectives At course completion, you will be able to: Describe the benefits of the Platform Designer system integration tool Recognize the design productivity benefits of using standard interfaces Understand the Custom interconnect generated by Platform Designer Skills Required Familiarity with FPGA/CPLD design flow Working knowledge of the Altera® Quartus® Prime software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OQSYS1000. FPGA_OQSYS1000. <p>Introduction to Platform Designer</p>