External Memory Interfaces in Agilex™ FPGAs (Part 2): Implementation - Same Course in Japanese: インテル Agilex™ デバイスのメモリー・インターフェイスの統合 97 Minutes This training is part 2 of 4. The Altera® Agilex™ family of FPGAs introduce brand new, higher performance architectures for implementing external memory interfaces, including DDR5 running at up to 5.6 Gbps on some devices. This part of the training discusses how to use the IP Parameter Editor in the Altera® Quartus® Prime Pro edition software or Platform Designer to create and parameterize the external memory interface IP for a standard FPGA or an SoC variant. It also shows how to constrain the IP in a device using either the Pin Planner or Interface Planner. Finally, resource sharing is presented to demonstrate how easy it is to implement multiple interfaces in a single device with minimal additional resource usage. Course Objectives At course completion, you will be able to: Parameterize the EMIF IP for Altera® Agilex™ FPGAs Constrain the IP to specific device resources Share device resources to implement multiple interfaces in a single device Skills Required Background in digital logic design Basic knowledge of memory interfaces and their implementation in Altera® FPGA devices Familiarity with the Altera® Quartus Prime software If the audio for the course does not start automatically, press pause and then play on the course player. A transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com. Reference Course Code: FPGA_OAGMEM102. FPGA_OAGMEM102. <p>External Memory Interfaces in Agilex FPGAs (Part 2): Implementation</p>