Critical Warning: *_p0_pin_map.tcl: Failed to find PLL clock for pins *:s0|*:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_IDLE - Critical Warning: *_p0_pin_map.tcl: Failed to find PLL clock for pins *:s0|*:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_IDLE Description You will see this critical warning message if you compile DDR3 Controller with UniPHY with the following assignment. In this case, the Quartus® II software cannot find pll_config_clock. set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF The Quartus II software will look for *:s0|*:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_IDLE to search pll_config_clock . The state will disappear if you disallow state machine generation. Thus, the Quartus® II software cannot find the clock. Resolution This problem has been fixed in Intel® Quartus® Prime Edition Software version 13.1. Custom Fields values: ['novalue'] Troubleshooting 2205800766 False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']