Error: <system name>.hps_0: "HPS-to-FPGA user <0,1,2> clock frequency" (S2FCLK_USER<0,1,2>CLK_FREQ) < frequency > is out of range: < osc1 frequency > - 100.0 - Error: <system name>.hps_0: "HPS-to-FPGA user <0,1,2> clock frequency" (S2FCLK_USER<0,1,2>CLK_FREQ) < frequency > is out of range: < osc1 frequency > - 100.0 Description Due to a problem in the Quartus® II software version 14.0, Qsys incorrectly restricts the minimum frequency of HPS User Clocks to the frequency of the external reference clock (OSC1/2). Resolution To work around this problem manually edit the PLL settings for the user clocks in the <BSP>/generated/pll_config.h file before running make to build the Software pre loader. Please see the Preloader Clocking Customization Page on www.Rocketboards.org for information on manually editing pll_config.h This problem has been resolved for the next release of the Quartus II Software Custom Fields values: ['novalue'] Troubleshooting 0 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue No plan to fix ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']