Why is there critical Design Assistant violation reported at Synthesis stage after Scalable Scatter-Gather DMA IP DMA PCIe Mode Example Design compilation? - Why is there critical Design Assistant violation reported at Synthesis stage after Scalable Scatter-Gather DMA IP DMA PCIe Mode Example Design compilation? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, critical Design Assistant violation may be reported after Scalable Scatter-Gather DMA IP DMA PCIe Mode Example Design compilation because of incorrect IP settings of GTS Reset Sequencer IP in the example design. The Enable PCIE and/or HPS USB3.1 only design parameter is not enabled. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 24.3, follow the steps below. Open the GTS Reset Sequencer IP instance in the example design and enable the Enable PCIE and/or HPS USB3.1 only design parameter. Save the change and regenerate HDL of the GTS Reset Sequencer IP. Open ssgdma_ed_top.sv, remove lines 603-605 on o_src_rs_grant, i_src_rs_priority, i_src_rs_req signals of GTS Reset Sequencer IP instance. Save the changes. Recompile the example design. Custom Fields values: ['novalue'] Errata 15016814150 False ['Modular Scatter-Gather DMA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']