Why is the output data clocked on the wrong edge of the clock? - Why is the output data clocked on the wrong edge of the clock? Description Due to a problem in the Quartus® II software version 15.0 and earlier, you may see the IO output register clocked on the incorrect edge. This problem may occur in Stratix® V designs when both the IO output register and IO output enable registers are clocked on the negative edge of the clock. You will see the data being incorrectly clocked on the rising edge. Resolution To work around this problem, either use core registers for the output register and output enable register or clock the registers on the rising edge of an inverted clock. Custom Fields values: ['novalue'] Troubleshooting NA False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']