The Design Assistant generates spurious warnings for Arria V designs that include 10GBASE-R PHY v12.0 megafunctions - The Design Assistant generates spurious warnings for Arria V designs that include 10GBASE-R PHY v12.0 megafunctions Description For designs that target the Arria V device family and that contain a 10GBASE-R PHY v12.0 megafunction, if you run the Design Assistant after fitting, the Design Assistant generates the following four critical warnings: Critical Warning (332012): Synopsys Design Constraints File file not found Critical Warning (308019): (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme Critical Warning (308060): (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains Critical Warning (308067): (High) Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains These warnings pertain to timing analysis, which the Quartus II software version 12.0 does not support for Arria V devices. Resolution For compilation and functional simulation, you may safely ignore these warnings. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0.1 12.0 ['Arria® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']