Error (175020): Illegal constraint of fractional PLL to the region (0, 98) to (0, 105): no valid locations in region - Error (175020): Illegal constraint of fractional PLL to the region (0, 98) to (0, 105): no valid locations in region Description You may see the above Quartus® II fitter error if a Stratix® V fractional PLL in "Operation mode = direct" is driven by the tx_clkout of a transceiver channel located in the lower triplet of a transceiver bank. This is a known problem with the Quartus II software which incorrectly enables "Operation mode = normal" in the fractional PLL. Resolution Manually set the fractional PLL Operation mode to direct through a QSF assignment. The following is an example of the QSF assignment: set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "pcie_pll:inst1|pcie_pll_0002:pcie_pll_inst|altera_pll:altera_pll_i|general[0].gpll" Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0.2 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']