Critical Warning: PLL clock output <PLL instance name>feeding the core has illegal output frequency of -0.1 MHz that must be less than <Frequency in MHz> - Critical Warning: PLL clock output <PLL instance name>feeding the core has illegal output frequency of -0.1 MHz that must be less than <Frequency in MHz> Description You may see this critical warning when using PLL counter cascading in the ALTPLL megafunction. PLL counter cascading allows two PLL output counters to be cascaded to increase the possible divider value. The resulting output clock can have a very low frequency. Due to a bug in the Quartus® II software, this critical warning will be generated by mistake. You can safely ignore this warning. Resolution Verify the PLL clock output frequency matches your design requirements by viewing the PLL Usage section of the Compilation Report. This issue is scheduled to be fixed in a future version of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'HardCopy™ III ASIC Devices', 'HardCopy™ IV E ASIC Devices', 'HardCopy™ IV GX ASIC Devices', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']