Final Timing Model Change: Stratix III DDR Input Functional Failure - Final Timing Model Change: Stratix III DDR Input Functional Failure Description Stratix III DDR input registers fail to capture edge-aligned input data correctly while the TimeQuest Timing Analyzer shows positive slack when you use the corner clock pin and corner PLL.The final timing model was changed for Stratix III devices by updating the delay for a path from the corner clock pin to the corner PLL. Resolution Designs utilizing the affected path on the affected Stratix III parts must rerun the TimeQuest Timing Analyzer. If new timing violations occur, you must rerun the Fitter. This issue was fixed in the Quartus II software version 10.0 SP1. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 10.0.1 10.0 ['Stratix® III FPGAs'] ['novalue'] ['novalue'] ['novalue']