Why does the Arria® 10, Cyclone® 10, and Stratix®10 HDMI FPGA IP Design Example fail to work when switching the resolution from FRL to TMDS mode? - Why does the Arria® 10, Cyclone® 10, and Stratix®10 HDMI FPGA IP Design Example fail to work when switching the resolution from FRL to TMDS mode? Description Due to a problem in the Arria® 10, Cyclone® 10 and Stratix®10 HDMI FPGA IP Design Example when using the Quartus® Prime Pro Edition Software v24.1 and earlier, you will observe rx_is_lockedtodata toggling when switching FRL to TMDS mode when using the HDMI FPGA IP Design Example. Resolution To workaround this problem, modify the mr_rx_rcfg_ctrl.v as shown below in bold. timeout_cntr_reset <= (current_state == IDLE) || ((current_state == RECONFIG_PLL_TMDS) && rxpll_tmds_rcfg_done) || ((current_state == WAIT_PLL_TMDS_LOCKED) && rxpll_tmds_locked && rxphy_analogreset_ack) || ((current_state == RECONFIG_RXPHY) && rxphy_rcfg_done) || ((current_state == WAIT_RXPHY_READY) && rxphy_ready) || ((current_state == WAIT_RXCORE_LOCKED) && (rxcore_locked)) || ((current_state == RXCORE_IS_LOCKED) && (rxcore_locked)); This problem is fixed beginning with version 24.3 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15015774771 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']