How long should I wait between subsequent transceiver dynamic reconfiguration Avalon Memory Mapped processes on Stratix V and Arria V transceiver devices? - How long should I wait between subsequent transceiver dynamic reconfiguration Avalon Memory Mapped processes on Stratix V and Arria V transceiver devices? Description When you start a transceiver dynamic reconfiguration processes on Stratix® V and Arria® V transceiver devices, the Reconfiguration Controller "busy" signal will assert high within 3 "mgmt_clk_clk" cycles. You should wait until after the Reconfiguration Controller "busy" signal goes low again before starting the next process. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']