Internal Error: Sub-system: CPLL, File: /quartus/periph/cpll/cpll_gen8.cpp - Internal Error: Sub-system: CPLL, File: /quartus/periph/cpll/cpll_gen8.cpp Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and earlier, you might see this internal error during the Place Stage when compiling the IOPLL FPGA IP. This internal error occurs when enabling the option " Refclk source is global clock" of the IOPLL FPGA IP. Resolution To work around the problem, modify the Verilog code in the submodule file <*>_altera_iopll_2000_<*>.v of the IOPLL FPGA IP as the followings: From .clkin_0_src("coreclkin"), to .clkin_0_src("ioclkin_0"), This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15018034387 False ['IOPLL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']