Quarter-rate DDR3 Designs Targeting Arria V Devices at 667 MHz May Fail Timing - Quarter-rate DDR3 Designs Targeting Arria V Devices at 667 MHz May Fail Timing Description This problem affects DDR3 products. Quarter-rate DDR3 designs targeting Arria V devices and running at 667 MHz may not meet timing requirements on the address and command and read capture paths. Resolution The workaround for this issue is to add the following constraint to the SDC file: if {} { foreach { ck_pin } { set_clock_uncertainty -from [get_clocks ] -to [get_clocks ] -add -hold 0.200 }} In addition, 800 MHz speed grade memory components are recommended. This issue will be fixed in a future release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1.1 ['Arria® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']