Why do I see a higher than 2ns PPS output accuracy error when using the Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP in Advanced accuracy mode? - Why do I see a higher than 2ns PPS output accuracy error when using the Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP in Advanced accuracy mode? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software Version 21.3, Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP may observe higher than the expected 2ns accuracy error on pps_pulse_per_second output in Advanced accuracy mode when the selected frequency of IOPLL scan clock is more than 1/2 of the frequency of the period clock. For a 100MHz scan clock, you might observe the problem with a period clock frequency lower than 200MHz. Basic accuracy mode is not impacted by this problem. Resolution To work around this problem, specify the scan clock frequency to half the period clock frequency or less. For the 156.25 MHz period clock, choose a scan clock with a frequency of 78.125MHz or lower. For the 125 MHz period clock, choose a scan clock with a frequency of 62.5MHz or lower. This problem has been fixed in version 23.3 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 15013772775 False ['Ethernet IEEE 1588 Time of Day Clock IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 21.3 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']