Error (10253): Verilog HDL Module Instantiation error at <design>.v(line #): cannot elaborate array of instances because the declaration for the instantiated module has not been analyzed - Error (10253): Verilog HDL Module Instantiation error at <design>.v(line #): cannot elaborate array of instances because the declaration for the instantiated module has not been analyzed Description This error may occur when synthesizing with the Quartus® II software version 6.1 or 7.0, if your module name matches the instance name. For example, in the following module called tribuf64bit , there is a module instantiation called tribuf8bit : module tribuf64bit (output [63:0] out, input [63:0] in, input enable); wire [63:0] out, in; wire enable; //array of eight 8-bit tri-state buffers; each instance is connected //to 8-bit part selects of the 64-bit vectors; tribuf8bit tribuf8bit[7:0] (out, in, enable); endmodule The instance name tribuf8bit is the same as the module name tribuf8bit . To work around this problem, change the name of the instance to something other than the module name. For example, change the instance name as follows: tribuf8bit inst_tribuf8bit[7:0] (out, in, enable); This issue is scheduled to be fixed in a future version of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']