Why does quarter rate DDR3 UniPHY-based controller design show low read efficiency? - Why does quarter rate DDR3 UniPHY-based controller design show low read efficiency? Description The low read efficiency is caused by one of the settings in the DDR3 controller for quarter rate design. When the read latency is longer (e.g: larger CAS latency number), the controller will stall internal read commands from executing because the maximum number of pending read commands is reached. Resolution The current workaround for this problem is to change the parameter MAX_PENDING_RD_CMD from 16 to 32 in the <instance_name>_c0.v file as follows: From MAX_PENDING_RD_CMD = 16 to MAX_PENDING_RD_CMD = 32 This problem is fixed starting with the Quartus® II software version 13.1. Custom Fields values: ['novalue'] Troubleshooting 1408030489 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 13.0 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']