Why does Nios® V processor simulation fail when using the generated VHDL testbench from Platform Designer? - Why does Nios® V processor simulation fail when using the generated VHDL testbench from Platform Designer? Description Due to a problem in the Quartus ® Prime Standard Edition software version 25.1, Nios ® V processor simulation may fail with the generated VHDL testbench system from Platform Designer for any processor design. This problem affects: All Altera ® FPGA device families in Quartus ® Prime Standard Edition software, and All Nios ® V processor variants (Nios ® V/g, Nios ® V/m, and Nios ® V/c processors). It is because the generation of the Nios ® V processor VHDL testbench system is not supported in Quartus ® Prime Standard Edition software version 25.1. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, please select “Verilog” at the “Create testbench simulation model” input option. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition software. Related Articles 3.3.1. Preparing Hardware Design for Simulation Custom Fields values: Troubleshooting 16028733950, 16028780469, 16028780568 ['Soft Embedded Processors RISC-V NIOS V (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 25.1 ['Arria® 10 FPGAs and SoCs', 'Arria® V FPGAs and SoCs', 'Arria® II FPGAs', 'Cyclone® 10 LP FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'MAX® 10 FPGAs', 'MAX® V CPLDs', 'MAX® II CPLDs', 'Stratix® V FPGAs', 'Stratix® IV FPGAs']