Why does the JESD204B Example Design fail to generate in simplex transmitter mode? - Why does the JESD204B Example Design fail to generate in simplex transmitter mode? Description In the JESD204B example design targetting Intel® Arria® 10 or Intel® Stratix® 10 devices, the ATX PLL component shares the same reference clock frequency with the CDR clock frequency. For duplex mode (Data path: Duplex), you can select a valid reference clock from the PLL/CDR Reference Clock Frequency drop-down menu in the IP parameter editor. For simplex TX mode (Data path: Transmitter), the drop-down menu is not available for selection. The example design generation will take the previous valid reference clock frequency from the drop-down. This may cause an error during example, design generation. Resolution To avoid this error for simplex TX example design generation, follow the sequence below when configuring the JESD204B IP parameters: Enter the desired Data rate. Choose a valid reference clock from PLL/CDR Reference Clock Frequency drop-down**. Select Data path: Transmitter Configure the rest of the parameters. ** Please refer to the Intel Arria® 10/Intel® Stratix® 10 Device Datasheet for a valid range of reference clock frequency for the ATX PLL. This problem is fixed starting with Intel® Quartus® Prime Pro Software version 17.1 Custom Fields values: ['novalue'] Troubleshooting FB: 490330; False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1 17.0 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']