Minimum Pulse Width Timing Failures for UniPHY External Memory Interfaces - Minimum Pulse Width Timing Failures for UniPHY External Memory Interfaces
Description Designs targeting Stratix V devices at speeds greater than 500MHz might experience minimum pulse width timing failure. Resolution There is no workaround for this issue.
Custom Fields values:
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Troubleshooting
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True
['novalue']
['FPGA Dev Tools Quartus II Software']
11.0.1
11.0
['Stratix® V FPGAs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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