Why does the R-tile AXI Multichannel DMA IP for PCI Express* Example Design (AXI-S Packet Generate/Check variant) generation fail with Enable User MSI-X IP is selected? - Why does the R-tile AXI Multichannel DMA IP for PCI Express* Example Design (AXI-S Packet Generate/Check variant) generation fail with Enable User MSI-X IP is selected? Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3, 25.3.1 and 26.1, Example Design generation fails for the R-Tile AXI Multichannel DMA IP for PCI Express* when: AXI-S Packet Generate/Check mode is selected Enable User MSI-X option is selected under the PCIe Settings --> MCDMA Settings tab The problem is observed a few minutes after clicking the Generate Example Design button. Quartus® Prime Pro Edition Software reports an error in the Generate Example Design Completed window and the Example Design is not generated successfully. An example of the message observed in the Generate Example Design Completed window is shown below: Error: add_connection GEN_CHK_M0.usr_msix DUT.user_msix: Cannot connect GEN_CHK_M0.usr_msix to DUT.user_msix. Error: Failed to generate example design example_design to: <path> This problem applies only to the AXI-S Packet Generator/Checker variant of the Example Design. The AXI Multichannel DMA IP itself can still be generated successfully when the Enable User MSI-X option is selected. Resolution To work around this problem, do not select the Enable User MSI-X option when generating the R-Tile AXI Multichannel DMA IP for PCI Express* Example Design. There is no other workaround for Quartus Prime Pro Edition Software versions 25.3, 25.3.1, and 26.1. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software. Custom Fields values: Troubleshooting QS-18966 novalue ['Interfaces PCIe'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex® 7 FPGAs and SoCs']