JPEG-LS-E: Lossless & Near-Lossless JPEG-LS Encoder - The JPEG-LS-E core is a low-power, high-efficient image compression engine compliant with JPEG-LS (ISO/IEC 14495-1). Based on the LOCO-I algorithm, it achieves compression ratios comparable or… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The JPEG-LS-E core implements a highly efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard. Based on LOCO-I (LOw COmplexity LOssless COmpression for Images), the JPEG-LS algorithm leads in numerically lossless compression efficiency, attaining compression ratios similar or superior to those obtained with more advanced algorithms such as JPEG 2000. JPEG-LS also enables hardware implementations with a much smaller silicon footprint and lower memory requirements, thanks to its lower computational complexity and line-based processing. Further, the Near-Lossless mode of the JPEG-LS standard makes higher compression ratios and visually lossless compressed images feasible, allowing the user to set the maximum acceptable difference between a reconstructed and an original image sample. The JPEG-LS-E core delivers the full compression efficiency of the standard in a compact and easy-to-use hardware block. The core interfaces to the system via standardized AMBA® interfaces: it accepts images and outputs compressed data via AXI4-Stream interfaces, and provides access to its control and status registers via a 32-bit APB interface. After its registers are programmed, the core can encode an arbitrary number of images without requiring any further assistance or action from the system. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface. The core is designed with industry best practices, and its reliability has been proven through both rigorous verification and silicon validation. The deliverables include a complete verification environment and a bit-accurate software model. Video and Image Processing Access Aerospace Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Industrial Medical Test Transportation Wireless JPEG-LS-E: Lossless & Near-Lossless JPEG-LS Encoder Key Features JPEG-LS Encoder delivers efficient lossless and near-lossless compression, supports up to 64Kx64K images, 16-bit samples, and 4 components. Offering Brief Yes Yes No Yes Encrypted Verilog Verilog Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U7OMAU What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist Ordering Information JPEG-LS-E a1JUi0000049U7OMAU Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-09-28T22:47:50.000+0000 The JPEG-LS-E core is a low-power, high-efficient image compression engine compliant with JPEG-LS (ISO/IEC 14495-1). Based on the LOCO-I algorithm, it achieves compression ratios comparable or superior to JPEG2000 in lossless mode, while requiring far less area & memory thanks to its low complexity & line-based processing. Its Near-Lossless mode enables higher compression ratios with visually lossless quality, letting users define the max pixel error. It delivers full JPEG-LS compression efficiency in a compact, easy-to-integrate hardware block. It connects through AMBA® interfaces: AXI4-Stream for image input & compressed output, & a 32-bit APB for control & status. Once configured, it can process unlimited images without host intervention, with optional metadata or timestamps inserted via a dedicated streaming port. The core’s robustness has been proven through extensive verification & silicon validation & is delivered with a full verification environment & bit-accurate SW model. Partner Solutions