Arria 10 EMIF on-chip debug - Arria 10 EMIF on-chip debug Hello, Question about on-chip debug of the Arria 10 EMIF (DDR4). I have built the system, custom board, used the EMIF debug toolkit, etc., everything is fine. And, as I understood from the "EMIF handbook vol. 3", I should be able to read the EMIF calibration data on-chip as well. I need this information to make sure the memory is connected correctly etc. The same manual states that I have to enable "soft NIOS processor" on the EMIF diagnostic tab to access the debug data? I can do that. But then the mystery begins. First of all, the Quartus generates time-limited .sof for me. That's the matter of IP licenses of some kind, I guess. But further, how can I get the data from that special EMIF debug NIOS to my application running on another NIOS? The debug only NIOS seems to capture the on-chip debug port and hide somewhere in EMIF. I don't quite understand the logic. Question: can I just expose the EMIF on-chip debug port in QSYS, connect it to my NIOS controlling the rest of the system and access the same data, recalibrate the memory, etc, as using the EMIF debug toolkit over the JTAG? And, do you provide any API for that? BR, Madis Arria10 10AX027E2F29 Quartus pro 21.1.0 Replies: Re: Arria 10 EMIF on-chip debug Hi Madis, Unfortunately the decoding method is known to Intel Engineering team for advance internal debug purpose only. I don't have any doc nor the knowledge to share with you. The only info assessible for external customer will be the info displayed in the toolkit itself. Thanks for your understanding. Regards, dlim Replies: Re: Arria 10 EMIF on-chip debug Hi, OK, I understand. My system is fine and running now, and I used the toolkit to tune the EMIF, nice SW. I just thought that using calibration pass/fail signals is a kind of diagnostics from the previous century. Getting some more insight into margins and or generate the eye diagram for diagnostic purposes would possibly allow us to issue an early failure warning during the normal system operation. So, if you have a document about the data log and how to decode it then maybe you can share it? BR, Madis Replies: Re: Arria 10 EMIF on-chip debug To answer your other question - No, we don't have any API to control the EMIF on chip debug feature. The end product of "EMIF on chip debug" feature is basically the "EMIF debug toolkit" itself. The toolkit decode the calibration data log and present it into user readable format Thanks. Regard, dlim Replies: Re: Arria 10 EMIF on-chip debug Hi, I don't recommend you to use "EMIF on chip debug" feature as it's mainly useful for Intel Internal debug only. Whatever calibration data log that you dump out won't be meaningful unless you know how to decode it. Instead, may I recommend you to monitor DDR4 IP interface "local_cal_success" and "local_cal_fail" status signal with your NIOS software program ? These 2 status signals is good enough to tell your system whether DDR4 calibration process pass or fail If unfortunately your system is really failing DDR4 calibration, then you can use EMIF debug toolkit to perform debugging and collect more debug info from there Thanks. Regards, dlim