No Image Output When DisplayPort Pixel Clock Is 3X or More Faster Than TX Link Clock - No Image Output When DisplayPort Pixel Clock Is 3X or More Faster Than TX Link Clock Description When you configure the DisplayPort TX core to any configurations that enable the pixel clock to run faster than the TX link clock by at least a factor of 3, the image may not display on the monitor. This issue is caused by the periodical overflow in the DCFIFO that crosses video data from pixel clock to link clock domain. For example, this issue will occur if you configure the TX core to 1 pixel per clock and 4 symbols per clock at RBR (1.62 Gbps) with 4 lanes to transmit 1080p60 at 24 bpp. In this particular case, the DCFIFO will overflow and you will not see the image output. Resolution To work around this issue, change the pixels per clock, symbols per clock, link rate, and lane count configurations to lower the ratio of pixel clock to TX link clock. For example, to transmit 1080p60 at 24 bpp, you can use 1 pixel per clock, 4 symbols per clock, HBR with 2 lanes so that the pixel clock is 148.5 MHz and TX link clock is 67.5 MHz. This issue is fixed in version 15.0 version of the DisplayPort IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 15.0 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']